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Quick Start Guide: For the Intel® Xeon Phi™ Coprocessor Developer

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This article makes recommendations for how a developer can get up to speed quickly on the Intel® Many Integrated Core (Intel® MIC) Architecture. This is one of three articles: For the Administrator, for the Developer, and for the Investigator.

Administrator– This is someone whose responsibility will be to administrate an Intel® Xeon Phi™ coprocessors, whether a single server with one or more cards, or a large cluster.

Developer– This is someone who will be programming on an Intel Xeon Phi coprocessor.

Investigator– This is someone who is evaluating whether their facility or staff should support the coprocessor. This also includes persons who desire to learn more about the coprocessor but who are not currently tasked to program or administer an Intel MIC system.

These articles make certain assumptions about what topics are most important to individuals in the different categories. For example, the documentation on cluster administration probably is not of interest to a developer. Similarly, the syntax and semantics of kmp_affinity is of little interest to an administrator. And though an investigator may be a programmer, they are unlikely to consider the syntax and semantics of the “pragma simd” annotation playing any significant role in an investigation of whether their facility should support an Intel Xeon Phi coprocessor cluster.

The following table lays out the most important categories that an administrator wants to know. References addressing those categories then follow. The intent of these references is not to be inclusive but only a good starting point. As an administrator, you will need to explore beyond these areas, but it is hoped that this article provides the beginnings of a path to help you along your way.

TERMINOLOGY AND NOTATION

MIC-IDZ – http://software.intel.com/mic-developer; this is the “Landing page” on the Intel® Developer Zone for Intel Many Integrated Core (Intel MIC) technical information.

AAA => BBB => CCC – This is a simple notation for navigating links, sections, documents, etc. Its intent is to be simple and clear but not precise. Even so, it should be obvious as to where to navigate next. For example, depending upon its context, “=> BBB” could mean “got to tab BBB”, “look under section BBB” or “open document BBB”.

 

Who is a Developer?

 

Someone who will be programming on an Intel Many Integrated Core (Intel MIC) architecture. The assumption is that they are most interested in:

  • Brief Introduction to the Intel MIC development environment
  • Programming models
  • Hardware architecture
  • Software stack
  • Coprocessor specific drivers and tools – Intel Manycore Platform Software Stack (Intel MPSS)
  • Compilers
  • Libraries
  • Tools
  • Examples and tutorials
  • SW Developer’s Guide
  • Programmer’s Guide
  • Optimization Guide
  • Getting help and other support

The list below describes how to navigate to resources that address these interests. A more direct URL is also given. Note that the URL and navigation may change at some point in the future.

We suggest using the navigation instructions. Even if the navigation changes slightly, you will still be able to get to the information. You will also discover the locations of other information that you will find useful as you continue to work with the coprocessor.

 

Technical Resources

 

Brief Introduction to the MIC Development Environment

Programming Models

Hardware Architecture

Software Stack (Intel MIC specific)

Intel Manycore Platform Software Stack (Intel MPSS): See “Coprocessor Specific Drivers and Tools” below.

Networking Infrastructure

The host and coprocessor use a standard Linux* OS and support most of the typical networking protocols, including NFS, IP, TCP/IP & UDP. Note that “support” does not imply they are in the default installation.

Coprocessor Specific Drivers and Tools

Languages available from Intel

Libraries available from Intel

Tools

Examples and Tutorials

  • Tutorials

    Navigation: MIC-IDZ => Programming => Programming => Programming and Compiling
    URL: http://software.intel.com/en-us/articles/programming-and-compiling-for-intel-many-integrated-core-architecture )
     
  • Code Samples on the Intel Developer Zone

    Navigation: MIC-IDZ => Training => Code Samples
     
  • Code Samples in the Compiler Installation

    Path: /opt/intel/composerxe/Samples/en_US – note that this location may differ on your system; also, the location is not guaranteed to remain
    Path: /opt/intel/composerxe/Documentation/en_US – for some tutorials
    Path: /opt/intel/mkl/examples/

SW Developer’s Guide

Navigation: MIC-IDZ => Programming => Programming => Intel Xeon Phi Coprocessor Software Developer’s Guide. Note that this is a System Software Developer’s Guide.
URL: http://software.intel.com/en-us/articles/intel-xeon-phi-coprocessor-system-software-developers-guide
Navigation: MIC-IDZ => Programming => Programming => Programming and Compiling
URL: http://software.intel.com/en-us/articles/programming-and-compiling-for-intel-many-integrated-core-architecture

Programmer Guides

Navigation: MIC-IDZ => Programming => Programming => Programming and Compiling
URL: http://software.intel.com/en-us/articles/programming-and-compiling-for-intel-many-integrated-core-architecture
Navigation: MIC-IDZ => Programming => Programming => Building Native Application
URL: http://software.intel.com/en-us/articles/building-a-native-application-for-intel-xeon-phi-coprocessors
Navigation: MIC-IDZ => Programming => Programming => Using OpenMP* extensions
URL: http://software.intel.com/en-us/articles/best-known-methods-for-using-openmp-on-intel-many-integrated-core-intel-mic-architecture

Optimization Guides

MIC-IDZ => Programming => Optimization
URL: http://software.intel.com/en-us/articles/optimization-and-performance-tuning-for-intel-xeon-phi-coprocessors-part-1-optimization
URL: http://software.intel.com/en-us/articles/optimization-and-performance-tuning-for-intel-xeon-phi-coprocessors-part-2-understanding

Getting help and other support


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