These free technical webinars cover tips and techniques that will help sharpen your development skills to create faster, more reliable applications. Technical experts will cover topics ranging from vectorization, code migration, code optimization, using advanced threading techniques (e.g., OpenMP 4.0, Intel® Cilk™ Plus, Intel® TBB), and error checking. Bring programming questions to the live session for our technical experts to answer. A replay of each webinar will be available shortly after the live session so you can share with those unable to attend the live session.
Times indicated are Pacific time. PST: Standard (UTC/GMT -8 hours), PDT: Daylight Savings (UTC/GMT -7 hours)
Upcoming Webinars
| Webinar Details | Description |
|---|---|
New Vectorization Features of the Intel Compiler Apr 7 9:00 A.M. Pacific Presenter: | The vectorization features of the Intel compiler continue to get more powerful with each succeeding version. In this webinar, we will look beyond the vectorization of simple loops over intrinsic data types, to examples involving STL (Standard Template Library) vectors; indirect addressing (gathers and scatters); multi-dimensional arrays, including data alignment; and explicit outer loop vectorization, using the SIMD feature of OpenMP 4.0. Code samples will include C, C++ and Fortran. |
Vectorize or Die – unlock performance secrets with data driven software design Apr 14 9:00 A.M. Pacific Presenter:
| The free ride of faster performance with increased clock speeds is long gone. Software must be both threaded and vectorized to fully utilize today’s and tomorrow’s hardware. But modernization is not without cost. Not all threading or vectorization designs are worthwhile. How do you choose which designs to implement without disrupting ongoing development? Learn how data driven threading and vectorization design can yield long term performance growth with less risk and more impact. |
Parallel programming models - tips and tricks Apr 21 9:00 A.M. Pacific Presenter:
| As computing advances, parallel architectures are becoming more common. In order to take advantage of parallel systems, software must adapt and use more parallelism. In this webinar, I will discuss various parallel programming models for shared memory and distributed memory parallelism, and give advice for how to utilize each of these models. I will also discuss how Intel® Advisor XE, Intel® VTune™ Amplifier XE, and Intel® Trace Analyzer and Collector can assist with adding parallelism to your programs or to improve your current parallelism. |
Fast, light weight, scalable MPI performance analysis May 5 9:00 A.M. Pacific Presenter:
| Developers of modern HPC applications face a challenge when scaling out their hybrid (MPI/OpenMP) applications. Cluster sizes continue to grow, the amount of analysis data collected can easily become overwhelming when going from 10s to 1000s of ranks and it’s tough to identify which are the key metrics to track. There is a need for a visual tool that aggregates the performance data in a simple and intuitive way, provides advice on next optimizations steps, and hones in on performance issues. In this webinar, we’ll discuss a brand new tool that helps quickly gather and analyze statistics up to 100,000 ranks. We’ll give examples of the type of information provided by the MPI Performance Snapshot including memory and counter usage, MPI and OpenMP imbalance analysis, and total communication vs. computation time. We’ll feature screenshots of the tool running in real-time and showcase some of its runtime and filtering capabilities. |
Respect programming models – manage Intel Xeon Phi’s in your Clusters for enhanced user experience May 12 9:00 A.M. Pacific Presenter:
| HPC cluster programming model number 1 has been MPI for the past 10 or more years. The Advent of coprocessors and accelerators forced many users to rethink their strategies and re-structure the code, even though a clever setup of Xeon Phi system allows to use them without being forced to do so. This webinar will present a number of techniques to help the system administrator with his task.
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3 Tuning Secrets for better OpenMP performance using Intel® VTune Amplifier XE May 19 9:00 A.M. Pacific Presenter:
| Parallelism delivers the capability High Performance Computing (HPC) requires. The parallelism runs across several layers: super scalar, vector instructions, threading and distributed memory with message passing. OpenMP* is a commonly used threading abstraction, especially in HPC. Many HPC applications are moving to a hybrid shared memory/distributed programming model where both OpenMP* and MPI* are used. This webinar focuses on the OpenMP parallel model, and particularly on profiling the performance of OpenMP-based applications. Intel supplies a powerful performance profiling tool, Intel® VTune™ Amplifier XE, that is quite handy for finding performance bottlenecks in OpenMP codes. In this webinar, we will go through the steps necessary to profile OpenMP applications, and will describe how you can quickly identify performance issues with task granularity, workload imbalance and synchronization using Intel® VTune™ Amplifier XE. |
Vectorizing Fortran using OpenMP 4.x - filling the SIMD lanes May 26 9:00 A.M. Pacific Presenter:
| The Intel® Fortran Composer XE adopted the OpenMP* 4.x Standard’s new SIMD clause and feature in 2014. The OpenMP SIMD directive is a portable and easy-to use feature, particularly for those already familiar with OpenMP. The SIMD feature allows Fortran programmer to more directly control vectorization and thereby extract maximum performance from modern Intel® Architecture Processors. Some existing knowledge of vectorization, memory alignment, and OpenMP is helpful but not necessary. Ronald W. Green from the Intel Fortran Support team at Intel will lead this discussion of Fortran OpenMP SIMD directives and use, vectorization, and optimizations that will get your development efforts powered. |