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Compiler, Architecture and Tools Conference - Program 2013

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CATC 2013 Program:

Day 1 November 19:

8:00 ISTRegistration and Breakfast
9:00 ISTKeynote:The Yin and Yang of Heterogenous Hardware: Can Software Survive?
Prof. Kathryn McKinley, Microsoft Research, USA
10:00 ISTbreak
Session 1: Programming Languages
10:20 ISTTowards a unified heterogeneous development model in Android
Alejandro Acosta, Francisco Almeida, La Laguna University, Spain
10:45 ISTCommon Low Level Intermediate Representation for 3D Graphics
Radosław Drabiński, Paweł Majewski, Krystian Matusiewicz, Konrad Trifunović, Marek Targowski, Intel, Poland
11:10 ISTA new Intermediate Representation standard for safe and portable code distribution to heterogeneous environments
Boaz Ouriel, Intel, Haifa
11:35 ISTbreak
Session 2: Runtime and Performance
11:55 ISTPushing the limits of work-stealing on Intel® Xeon Phi™ within Intel® Threading Building Blocks library
Anton Malakhov, Intel, Russia
12:20 ISTThreads are Evil, Tasks are Good: Towards a Unified Resource Management Framework
Mats Brorsson , Georgios Varisteas, KTH Royal Institute of Technology and SICS, Sweden
12:45 ISTRecreating customer workloads
Sharon Barner, Eitan Farchi, Andrei Heilper, Sergey Novikov, IBM, Israel
13:10 ISTLunch
14:10 ISTKeynote: Auto-parallelization reloaded, avoiding groundhog day
Prof. Michael O'Boyle, University of Edinburgh, UK
15:10 ISTbreak
Session 3: HW/SW co-optimization
15:30 IST1K Cores FPGA Shared Memory Architecture for Embedded Systems
Yosi Ben Asher, Yousef Shajrawi, Yacove Gendel, Oren Segal, U. of Haifa, IBM, Israel and UMass Lowell, USA
15:55 ISTAmalgamated Transactions: Executing Long Transactions Mostly in Hardware
Yehuda Afek, Alex Matveev, Nir Shavit, Tel Aviv U, Israel and MIT, USA
16:20 ISTCompiler Assessed CPU Power Management
Jawad Haj-Yihia, Yosi Ben-Asher, Efraim Rotem, U. of Haifa and Intel, Israel
16:45 ISTSpeculative Dynamic Vectorization to Assist Static Vectorization in a HW/SW Co-designed Environment
Rakesh Kumar, Alejandro Martínez, Antonio González, U. Politècnica de Catalunya and Intel Barcelona, Spain
17:10 ISTClosing Remarks

Day 2 November 19:

8:00 ISTRegistration and Breakfast
9:00 ISTKeynote: The Yin and Yang of Heterogenous Hardware: Can Software Survive?
Prof. Kathryn McKinley, Microsoft Research, USA
10:00 ISTbreak
Session 4: Programming Languages
10:20 ISTTowards a unified heterogeneous development model in Android
Alejandro Acosta, Francisco Almeida, La Laguna University, Spain
10:45 ISTCommon Low Level Intermediate Representation for 3D Graphics
Radosław Drabiński, Paweł Majewski, Krystian Matusiewicz, Konrad Trifunović, Marek Targowski, Intel, Poland
11:10 ISTA new Intermediate Representation standard for safe and portable code distribution to heterogeneous environments
Boaz Ouriel, Intel, Haifa
11:35 ISTbreak
Session 5: Runtime and Performance
11:55 ISTPushing the limits of work-stealing on Intel® Xeon Phi™ within Intel® Threading Building Blocks library
Anton Malakhov, Intel, Russia
12:20 ISTThreads are Evil, Tasks are Good: Towards a Unified Resource Management Framework
Mats Brorsson , Georgios Varisteas, KTH Royal Institute of Technology and SICS, Sweden
12:45 ISTRecreating customer workloads
Sharon Barner, Eitan Farchi, Andrei Heilper, Sergey Novikov, IBM, Israel
13:10 ISTLunch
14:10 ISTKeynote:Auto-parallelization reloaded, avoiding groundhog day
Prof. Michael O'Boyle, University of Edinburgh, UK
15:10 ISTbreak
Session 6: HW/SW co-optimization
15:30 IST1K Cores FPGA Shared Memory Architecture for Embedded Systems
Yosi Ben Asher, Yousef Shajrawi, Yacove Gendel, Oren Segal, U. of Haifa, IBM, Israel and UMass Lowell, USA
15:55 ISTAmalgamated Transactions: Executing Long Transactions Mostly in Hardware
Yehuda Afek, Alex Matveev, Nir Shavit, Tel Aviv U, Israel and MIT, USA
16:20 ISTCompiler Assessed CPU Power Management
Jawad Haj-Yihia, Yosi Ben-Asher, Efraim Rotem, U. of Haifa and Intel, Israel
16:45 ISTSpeculative Dynamic Vectorization to Assist Static Vectorization in a HW/SW Co-designed Environment
Rakesh Kumar, Alejandro Martínez, Antonio González, U. Politècnica de Catalunya and Intel Barcelona, Spain
17:10 ISTClosing Remarks

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