The 60 Pin Debug Port (XDP) Specification Document (DPS) specifies the open chassis Platform requirements to implement a 60 Pin XDP connector to use PHG XDP debug tools and third party vendors that support the 60 Pin XDP interface.
Since Skylake platform, internal boards that will be used as a reference to external customers are required to implement 1 X Merged 60 Pin XDP Connector.
Symptom: If customer implements a non-shared JTag design, you will address some issues, such as can’t create connection, or can’t halt the target, etc.
There is a work around below for this kind of systems.
About the detail steps, please see the attached file.
